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NJU6631A preliminary 16-character 1-line dot matrix lcd controller driver general description package outline the NJU6631A is a 1 chip dot matrix lcd controller driver for up to 16-character 1-line or 8-character 2-line display. it contains microprocessor interface circuits, instruction decoder controller, character generator rom/ram and common and segment drivers. the bleeder resistance generates for lcd bias voltage internally. the cr oscillator incorporates c and r, therefore no external components for oscillation are required. the microprocessor interface circuits which operate 2mhz frequency, can be connected directly to 4bit/8bit microprocessor. the character generator consists of 9,600 bits rom and 32 x 5 bits ram. the standard version rom is coded with 192 characters including capital and small letter fonts. the 16-common and 40-segment drives up to 16- character 1-line lcd panels which divided two common electrode blocks. the rectangle outlook is very applicable to cog or slim tcp. features 16-character 1-line dot matrix lcd controller driver 4/8 bit microprocessor direct interface display data ram - 16 x 8 bits : maximum 16-character 1-line display character generator rom - 9,600 bits : 240 characters for 5 x 8 dots character generator ram - 32 x 5 bits : 4 patterns(5 x 8 dots) microprocessor can access to display data ram and character generator ram high voltage lcd driver : 16-common / 40-segment duty ratio : 1/16 duty number of maximum display characters : 16-character useful instruction set clear display, return home, display on/off cont, cursor on/off cont, display blink, cursor shift, character shift, common and segment driver location order select function(pin configuration mode a / mode b) power on initialize / hardware reset function bleeder resistance on-chip oscillation circuit on-chip low power consumption operating voltage --- +5v package outline --- bumped chip c-mos technology 31.mar,2000 ver.1 NJU6631Ach
NJU6631A pad location chip size : 3.58mm x 1.68mm bump size : 90um x 55um chip center : x=0um, y=0um bump height : 17.5um typ. bump material : au block diagram cr osc power on reset display data ram (dd ram) 16x8bits instruction decoder(id) 1 18 31 74 y x reset osc 1 osc 2 rs r/w e db 4 db 7 db 0 db 3 4 4 address counter(ac) cursor blink cont. 16bit shift reg. common driver 40bit latch segment driver timing gen. character generator ram (cg ram) 32x5bits character generator rom (cg rom) 9,600bits busy flag parallel to serial converter 40bit shift reg. v ss v dd v 2 v 3 v 5 v 1 v 4 r 1 r 1 r 1 r 1 r 1 com 1 com 16 seg 1 seg 40 8 8 8 8 7 7 7 8 5 7 5 8 8 5 5 16 16 40 40 i/o buffer lcd driver instruction reg.(ir) data reg. (dr)
NJU6631A pad coordinates chip size 3.58 1.68mm(chip center x=0um,y=0um) pad name center pad name center pin configuration pin configuration pad no. mode a mode b x=(um) y=(um) pad no. mode a mode b x=(um) y=(um) 1 dummy1 dummy1 -1501 -680 44 seg 12 seg 29 543 690 2 v dd v dd -1426 -680 45 seg 13 seg 28 473 690 3 v dd v dd -1353 -680 46 seg 14 seg 27 403 690 4 v dd v dd -1281 -680 47 seg 15 seg 26 333 690 5 v 5 v 5 -1138 -680 48 seg 16 seg 25 263 690 6 v 5 v 5 -1066 -680 49 seg 17 seg 24 193 690 7 v 5 v 5 -993 -680 50 seg 18 seg 23 123 690 8 v 3 v 3 -844 -680 51 seg 19 seg 22 53 690 9 v 2 v 2 -614 -680 52 seg 20 seg 21 -17 690 10 reset reset -98 -680 53 seg 21 seg 20 -87 690 11 rs rs 132 -680 54 seg 22 seg 19 -157 690 12 r/w r/w 361 -680 55 seg 23 seg 18 -227 690 13 e e 591 -680 56 seg 24 seg 17 -297 690 14 db 0 db 0 824 -680 57 seg 25 seg 16 -367 690 15 db 1 db 1 1091 -680 58 seg 26 seg 15 -437 690 16 db 2 db 2 1328 -680 59 seg 27 seg 14 -507 690 17 dummy2 dummy2 1406 -680 60 seg 28 seg 13 -577 690 18 db 3 db 3 1630 -486 61 seg 29 seg 12 -647 690 19 db 4 db 4 1630 -416 62 seg 30 seg 11 -717 690 20 db 5 db 5 1630 -322 63 seg 31 seg 10 -787 690 21 db 6 db 6 1630 -253 64 seg 32 seg 9 -857 690 22 db 7 db 7 1630 -160 65 seg 33 seg 8 -927 690 23 com 1 com 9 1630 -13 66 seg 34 seg 7 -997 690 24 com 2 com 10 1630 57 67 seg 35 seg 6 -1067 690 25 com 3 com 11 1630 127 68 seg 36 seg 5 -1137 690 26 com 4 com 12 1630 197 69 seg 37 seg 4 -1207 690 27 com 5 com 13 1630 267 70 seg 38 seg 3 -1277 690 28 com 6 com 14 1630 337 71 seg 39 seg 2 -1347 690 29 com 7 com 15 1630 407 72 seg 40 seg 1 -1417 690 30 com 8 com 16 1630 477 73 dummy5 dummy5 -1501 690 31 dummy3 dummy3 1459 690 74 com 16 com 8 -1630 402 32 dummy4 dummy4 1383 690 75 com 15 com 7 -1630 332 33 seg 1 seg 40 1313 690 76 com 14 com 6 -1630 262 34 seg 2 seg 39 1243 690 77 com 13 com 5 -1630 192 35 seg 3 seg 38 1173 690 78 com 12 com 4 -1630 122 36 seg 4 seg 37 1103 690 79 com 11 com 3 -1630 52 37 seg 5 seg 36 1033 690 80 com 10 com 2 -1630 -18 38 seg 6 seg 35 963 690 81 com 9 com 1 -1630 -88 39 seg 7 seg 34 893 690 82 osc 1 osc 1 -1630 -230 40 seg 8 seg 33 823 690 83 osc 2 osc 2 -1630 -300 41 seg 9 seg 32 753 690 84 v ss v ss -1630 -370 42 seg 10 seg 31 683 690 85 v ss v ss -1630 -443 43 seg 11 seg 30 613 690 86 v ss v ss -1630 -515 note) dummy1 dummy5 are dummy pad.
NJU6631A terminal description pad no. pin configuration mode a mode b symbol function 2,3,4 2,3,4 v dd power source (+5v) 84,85,86 84,85,86 v ss power source ( 0v) 9,8, 7,6,5 9,8, 7,6,5 v 2 ,v 3 , v 5 lcd driving power source 82 83 82 83 osc 1 osc 2 oscillation frequency adjust terminals. normally open. (oscillation c and r are incorporated, osc freq.=270khz) for external clock operation, the clock should be input on osc1. 11 11 rs register selection signal input ?0? : instruction register (writing) busy flag (reading) ?1? : data register (writing/reading) 12 12 r/w read/write selection signal input ?0? : write, ?1? : read 13 13 e read/write activation signal input 22 19 22 19 db 7 db 4 3-state data bus (upper) to transfer the data between mpu and NJU6631A db 7 is also used for the busy flag reading. 18 14 18 14 db 3 db 0 3-state data bus (lower) to transfer the data between mpu and NJU6631A these bus are not used in the 4-bit operation. 23 30 81 74 81 74 23 30 com 1 com 8 com 9 com 16 lcd common driving signal terminals common driver location order select as shown in table 4. pin configuration mode a : m0=0 / mode b : m0=1. 33 72 72 33 seg 1 seg 40 lcd segment driving signal terminals segment driver location order select as shown in table 4. pin configuration mode a : m0=0 / mode b : m0=1. 10 10 reset reset terminal. when the ?l? level input over than 1.2ms to this terminal the system will be reset. (f osc =270khz)
NJU6631A functional description (1) description for each blocks (1-1) register the NJU6631A incorporates two 8-bit registers, an instruction register (ir) and a data register (dr). the register (ir) stores instruction codes such as ?clear display? and ?return home?, and address data for display data ram (dd ram) and character generator ram (cg ram). the mpu can write the instruction code and address data to the register (ir), but it cannot read out from the register (ir). the register (dr) is a temporary stored register, the data stored in the register (dr) is written into the dd ram or cg ram and read out from the dd ram or cg ram. the data in the register (dr) written by the mpu is transferred automatically to the dd ram or cg ram by internal operation. when the address data for the dd ram or cg ram is written into the register (ir), the addressed data in the dd ram or cg ram is transferred to the register (dr). by the mpu read out the data in the register (dr), the data transmitting process is performed completely. after reading the data in the register (dr) by the mpu, the next address data in the dd ram or cg ram is transferred automatically to the register (dr) to provide for the next mpu reading. these two registers are selected by the selection signal rs as shown below : table 1. shows register operation controlled by rs and r/w signals. table 1. register operation rs r/w selected register operation 0 0 write 0 1 ir read busy flag (db 7 ) and address counter (db 0 db 6 ) 1 0 write (dr to dd ram or cg ram) 1 1 dr read (dd ram or cg ram to dr) (1-2) busy flag (bf) when the internal circuits are in the operation mode, the busy flag is "1", and any instruction reading is inhibited. the busy flag (bf) is output at db 7 when rs="0" and r/w="1" as shown in table 1. the next instruction should be written after busy flag (bf) goes to "0". (1-3) address counter (ac) the address counter (ac) addressing the dd ram and cg ram. when the address setting instruction is written into the register (ir), the address information is transferred from register (ir) to counter (ac). the selection of either the dd ram or cg ram is also determined by this instruction. after writing (or reading) the display data to (or from) the dd ram or cg ram, the counter (ac) increments (or decrements) automatically. the address data in the counter (ac) is output from db 6 db 0 when rs="0" and r/w="1" as shown in table 1. (1-4) display data ram (dd ram) the display data ram (dd ram) consists of 16 x 8 bits, stores up to 16-character display data represented in 8-bit code. the dd ram address data set in the address counter (ac) is represented in hexadecimal. higher order bit lower order bit (example) dd ram address ?08? ac ac 6 ac 5 ac 4 ac 3 ac 2 ac 1 ac 0 0 0 0 1 0 0 0 hexadecimal 0 8 hexadecimal
NJU6631A (1-4-1) 16-character 1-line display the NJU6631A has two kinds of addressing mode called "addressing mode 1" and "addressing mode 2" which is determined by the function set instruction (a= 0 and 1). "addressing mode 1" is using consecutive address of (00) h through (0f) h for front half 8-character and last half 8-character. "addressing mode 2" is not using consecutive address likes as (00) h through (07) h and (40) h through (47) h for front half 8-character and last half 8-character respectively. 16-character 1-line and 8 character 2-line are also determined by the function set instruction (m1= 0 and 1). -the relation between dd ram address and display position on the lcd is shown below. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 display position 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f dd ram address (hexadecimal) when the display shift is performed, the dd ram address changes as follows: (left shift display) (00) 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 00 (right shift display) 0f 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e (0f) -the relation between dd ram address and display position on the lcd is shown below. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 display position 00 01 02 03 04 05 06 07 40 41 42 43 44 45 46 47 dd ram address (hexadecimal) when the display shift is performed, the dd ram address changes as follows: (left shift display) (00) 01 02 03 04 05 06 07 40 41 42 43 44 45 46 47 00 (right shift display) 47 00 01 02 03 04 05 06 07 40 41 42 43 44 45 46 (47) com 1 com 8 com 9 com 16 com 1 com 8 com 9 com 16
NJU6631A (1-4-2) 8-character 2-line -the relation between dd ram address and display position on the lcd is shown below. 1 2 3 4 5 6 7 8 display position 1st line 00 01 02 03 04 05 06 07 dd ram address 2nd line 08 09 0a 0b 0c 0d 0e 0f (hexadecimal) when the display shift is performed, the dd ram address changes as follows: (left display shift) 1st line(00) 01 02 03 04 05 06 07 08 2 nd line(08) 09 0a 0b 0c 0d 0e 0f 00 (right display shift) 1st line 0f 00 01 02 03 04 05 06 (07) 2nd line 07 08 09 0a 0b 0c 0d 0e (0f) -the relation between dd ram address and display position on the lcd is shown below. 1 2 3 4 5 6 7 8 display position 1st line 00 01 02 03 04 05 06 07 dd ram address 2nd line 40 41 42 43 44 45 46 47 (hexadecimal) when the display shift is performed, the dd ram address changes as follows: (left display shift) 1st line(00) 01 02 03 04 05 06 07 08 2 nd line(40) 41 42 43 44 45 46 47 00 (right display shift) 1st line 47 00 01 02 03 04 05 06 (07) 2nd line 07 40 41 42 43 44 45 46 (47) com 1 com 8 com 9 com 16 com 1 com 8 com 9 com 16
NJU6631A (1-5) character generator rom (cg rom) the character generator rom (cg rom) generates 5 x 8 dots character pattern represented in 8-bit character codes. the storage capacity is up to 240 kinds of 5 x 8 dots character pattern. the correspondence between character code and standard character pattern of NJU6631A is shown in table 2. user-defined character pattern (custom font) are also available by mask option.
NJU6631A table 2. cg rom character pattern (rom version -02)
NJU6631A (1-6) character generator ram (cg ram) the character generator ram (cg ram) can store any kinds of character pattern in 5 x 7 dots written by the user program to display user?s original character pattern. the cg ram can store 4 kinds of character in 5 x 7 dots mode. to display user?s original character pattern stored in the cg ram, the address data (00) h (03) h should be written to the dd ram as shown in table 2. table 3. shows the correspondence among the character pattern, cg ram address and data. table 3. correspondence of cg ram address, dd ram character code and cg ram character pattern (5 x 7 dots). character code (dd ram data) cg ram address character pattern (cg ram data) 7 6 5 4 3 2 1 0 4 3 2 1 0 4 3 2 1 0 cursor position 0 0 0 1 0 0 0 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 1 1 0 0 1 0 0 0 0 0 0 * * 0 1 0 1 1 0 0 1 1 1 1 1 character pattern 1 0 1 0 0 1 0 0 example (2) 1 1 0 0 0 1 0 0 1 1 1 0 0 0 0 0 cursor position 0 0 0 0 0 1 * : don?t care 0 0 0 0 * * 1 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1 notes : 1.character code bits 0 to 1 correspond to the cg ram address 3 and 4 (2 bits : 4 patterns) 2.cg ram address 0, 1 and 2 designate character pattern line position. the 8th line is the cursor position and the display is performed by logical or with cursor. therefore, in case of the cursor display, the 8th line should be "0". if there is "1" in the 8th line, the bit "1" is always displayed on the cursor position regardless of cursor existence. 3.character pattern row position correspond to the cg ram data bits 0 to 4 are shown above. the bits 5 to 7 of the cg ram do not exist. 4.cg ram character patterns are selected when character code bits 4 to 7 are all "0" and it is addressed by character code bits 0 to 1. therefore, the address (00) h , (04) h , (08) h and (0c) h , select the same character pattern as shown in table 2 and table 3. 5."1" for cg ram data corresponds to display on and "0" to display off.
NJU6631A (1-7) timing generator the timing generator generates a timing signals for the dd ram, cg ram, cg rom and other internal circuits operation. ram read timing for the display and internal operation timing for mpu access are separately generated, so that they may not interfere with each other. therefore, when the data write to the dd ram for example, there will be no undesirable influence, such as flickering, in areas other than the display area. (1-8) lcd driver lcd driver circuits consist of 16-common driver and 40-segment driver. the 40 bits of character pattern data are shifted in the shift-register and latched when the 40 bits shift performed completely. this latched data controls display driver to output lcd driving waveform. (1-9) cursor blinking control circuit this circuits controls cursor on/off and cursor position character blinks. the cursor or blinks appear in the digit residing at the dd ram address set in the address counter (ac). when the address counter is (04) h , a cursor position is shown as follows : ac 6 ac 5 ac 4 ac 3 ac 2 ac 1 ac 0 ac 0 0 0 0 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 display position 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f dd ram address (hexadecimal) cursor position note the cursor or blinks appear when the address counter (ac) selects the cg ram. but the displayed the cursor and blink are meaningless. if the ac storing the cg ram address data, the cursor and blink are displayed in the meaningless position.
NJU6631A (2) power on initialization by internal circuits (2-1) initialization by internal reset circuits the NJU6631A is automatically initialized by internal power on initialization circuits when the power is turned on. in the internal power on initialization, following instructions are executed. during the internal power on initialization, the busy flag (bf) is "1" and this status is kept 10 ms after v dd rises to 4.5v. initialization flow is shown below : dl=1 : 8-bit long interface data a=0 : addressing mode 1 m0=0 : pin configuration mode a m1=0 : 16-character 1-line d=0 : display off c=0 : cursor off b=0 : cursor blink off i/d=1 : increment by 1 s=0 : no shift (2-2) initialization by hardware the NJU6631A incorporates reset terminal to initialize the all system. when the "l" level input over 1.2ms to the reset terminal, reset sequence is executed. in this time, busy signal output during 10ms after reset terminal goes to "h". - reset circuit - timing chart clear display function set display on/off control entry mode set c rst counter q s r q power on reset reset system clock system reset rs-f/f external reset si g nal counter output rs-f/f output busy over than 1.2ms 10ms if the condition of power supply rise time described in the electrical characteristics is not satisfied, the internal power on initialization circuits will not operate and initialization will not be performed. in this case the initialization by mpu software is required. note internal reset signal
NJU6631A (3) instruction the NJU6631A incorporates two registers, an instruction register (ir) and a data register (dr). these two registers store control information temporarily to allow interface between NJU6631A and mpu or peripheral ics operating different cycles. the operation of NJU6631A is determined by this control signal from mpu. the control information includes register selection signals (rs), read/write signals (r/w) and data bus signals (db 0 to db 7 ). table 4. shows each instruction and its operating time. note) the execution time mentioned in table 4. based on fcp or fosc=270khz. if the oscillation frequency is changed, the execution time is also changed. table 4. table of instructions code instructions rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 description exec time maker test 0 0 0 0 0 0 0 0 0 0 all ?0? code is using for make r testing. - clear display 0 0 0 0 0 0 0 0 0 1 display clear and sets dd ram address 0 in ac. 1.52ms return home 0 0 0 0 0 0 0 0 1 * sets dd ram address 0 in ac and returns display being shifted to original position. dd ram contents remain unchanged. 37us entry mode set 0 0 0 0 0 0 0 1 i/d s sets cursor move direction and specifies shift of display are performed in data read/write. i/d=1:increment, i/d=0:decrement s=1:accompanies display shift. 37us display on/off control 0 0 0 0 0 0 1 d c b sets of display on/off(d), curso r on/off(c) and blink of curso r position character(b). 37us cursor or display shift 0 0 0 0 0 1 s/c r/l * * moves cursor and shifts displa y without changing dd ram contents s/c=1 : display shift s/c=0 : cursor shift r/l=1 : shift to the right r/l=0 : shift to the left 56us function set 0 0 0 0 1 dl a * m1 m0 sets interface data length(dl), display address mode(a). dl=1 : 8 bits, dl=0 : 4 bits a=0 : addressing mode 1 a=1 : addressing mode 2 m1=0: 16-character 1-line m1=1: 8-character 2-line m0=0: pin configuration mode a m0=1: pin configuration mode b 37us set cg ram address 0 0 0 1 * a cg sets cg ram address. after this instruction, the data is transferred on cg ram. 37us set dd ram address 0 0 1 a dd sets dd ram address. after this instruction, the data is transferred on dd ram. 37us ac dd read busy flag & address 0 1 bf * * ac cg reads busy flag and ac contents. bf=1 : internally operating bf=0 : can accept instruction 0us write data(dd ram) write data to cg or dd ram 1 0 * * * write data(cg ram) writes data into cg or dd rams. 37us read data(dd ram) read data to cg or dd ram 1 1 * * * read data(cg ram) reads data from cg or dd rams. 56us explanation of abbreviation dd ram : display data ram, cg ram : character generator ram a cg : cg ram address, a dd : dd ram address, corresponds to cursor address ac : address counter used for both of dd and cg rams * = don?t care
NJU6631A (3-1) description of each instructions (a) maker test rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 0 0 0 0 0 0 0 all "0" code in 4-bit length is using for device testing mode (only for maker). therefore, please avoid all "0" input or no meaning enable signal input at data "0". (especially please pay attention the output condition of enable signal when the power turns on.) all "0" code in 8-bit length is usable for nop (not operating instruction). (b) clear display rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 0 0 0 0 0 0 1 clear display instruction is executed when the code "1" is written into db 0 . when this instruction is executed, the space code (20) h is written into every dd ram address, the dd ram address 0 is set into the address counter and entry mode is set increment. if the cursor or blink are displayed, they are returned to the left end of the lcd. the s of entry mode does not change. note: the character pattern for character code (20) h must be blank code in the user-defined character pattern(custom font). (c) return home rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 0 0 0 0 0 1 * * = don?t care return home instruction is executed when the code "1" is written into db 1 . when this instruction is executed, the dd ram address 0 is set into the address counter. display is returned its original position if shifted, the cursor or blink are returned to the left end of the lcd, if the cursor or blink are on the display. the dd ram contents do not change. (d) entry mode set rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 0 0 0 0 1 i/d s entry mode set instruction which sets the cursor moving direction and display shift on/off, is executed when the code "1" is written into db 2 and the codes of (i/d) and (s) are written into db 1 (i/d) and db 0 (s), as shown below. (i/d) sets the address increment or decrement, and the (s) sets the entire display shift in the dd ram writing. i/d function 1 address increment : the address of the dd or cg ram increment (+1) when the read/write, and the cursor or blink move to the right. 0 address decrement : the address of the dd or cg ram decrement (-1) when the read/write, and the cursor or blink move to the left. s function 1 entire display shift. the shift direction is determined by i/d : shift to the left at i/d=1 and shift to the right at the i/d=0. the shift is operated only for the character, so that it looks as if the cursor stands still and the display moves. the display does not shift when reading from the dd ram and writing/reading into/from cg ram. 0 the display does not shifting.
NJU6631A (e)display on/off control rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 0 0 0 1 d c b display on/off control instruction which controls the display on/off, the cursor on/off and the cursor position character blink, is executed when the code "1" is written into db 3 and the codes of (d), (c) and (b) are written into db 2 (d), db 1 (c) and db 0 (b), as shown below. d function 1 display on. 0 display off. in this mode, the display data remains in the dd ram so that it is retrieved immediately on the display when the d change to 1. c function 1 cursor on. the cursor is displayed by 5 dots on the 8th line. 0 cursor off. even if the display data write, the i/d etc does not change. b function 1 the cursor position character is blinking. blinking rate is 303.4ms at or f osc =270khz. the blink is displayed alternatively with all on (it means all black) and characters display. the cursor and the blink can be displayed simultaneously. 0 the character does not blink. cursor character font 5 x 7 dots alternating display (1) cursor display example (2) blink display example ( ) cursor / display shift rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 0 0 1 s/c r/l * * * = don?t care the cursor/display shift instruction shifts the cursor position or display to the right or left without writing or reading display data. this function is used to correct or search the display. the contents of address counter (ac) does not change by operation of the display shift only. this instruction is executed when the code "1" is written into db 4 and the codes of (s/c) and (r/l) are written into db 3 (s/c) and db 2 (r/l), as shown below. s/c r/l function 0 0 shifts the cursor position to the left. ((ac) is decremented by 1) 0 1 shifts the cursor position to the right. ((ac) is incremented by 1) 1 0 shifts the entire display to the left and the cursor follows it. 1 1 shifts the entire display to the right and the cursor follows it.
NJU6631A ( ) function set rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 0 1 dl a * m1 m0 * = don?t care function set instruction which sets the interface data length, the addressing mode for the dd ram, 1-line or 2-line display, and pin configuration mode, is executed when the code "1" is written into db 5 and the codes of (dl), (a), (m1) and (m0) are written into db 4 (dl), db 3 (a), db 1 (m1) and db 0 (m0), as shown below (character font is fixed 5 x 7 dots). (dl) sets the interface data length, (a) sets the dd ram address mode (00) h through (0f) h or (00) h through (07) h and (40) h through (47) h , (m1) sets the number of display line either the 1-line or 2-line display, and (m0) sets the pin configuration for common and segment drivers as shown in coordinates. dl function 1 set the interface data length to 8 bits (db 7 to db 0 ). 0 set the interface data length to 4 bits (db 7 to db 4 ). the data must be sent or received twice. a function 0 set the addressing mode 1 for the dd ram. 1 set the addressing mode 2 for the dd ram. m1 function 0 set the 16-character 1-line display. 1 set the 8-character 2-line display. m0 function 0 set the pin configuration mode a for common and segment driver. 1 set the pin configuration mode b for common and segment driver. refer to coordinates (h) set cg ram address rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 0 1 * a a a a a * = don?t care higher order bit lower order bit set cg ram address instruction is executed when the code "1" is written into db 6 and the address is written into db 4 to db 0 as shown above. the address data mentioned by binary code "aaaaa" is written into the address counter (ac) together with the cg ram addressing condition. after this instruction execution, the data writing/reading is performed into/from the cg ram. (i) set dd ram address rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 0 1 a a a a a a a higher order bit lower order bit set dd ram address instruction is executed when the code "1" is written into db 7 and the address is written into db 6 to db 0 as shown above. the address data mentioned by binary code "aaaaaaa" is written into the address counter (ac) together with the dd ram addressing condition. after this instruction, the data writing/reading is performed into/from the dd ram. note : when the "addressing mode 1" selection, (00) h through (0f) h are available but (10) h through (7f) h are ignored. when the "addressing mode 2" selection, (00) h through (07) h and (40) h through (47) h are available but (08) h through (3f) h and (48) h through (7f) h are ignored. this function set instruction must be performed at the head of the program prior to all other existing instructions (except busy flag/address read). this function set instruction can not be executed afterwards unless the interface data length change. note
NJU6631A (j) read busy flag & address rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 0 1 bf a a a a a a a higher order bit lower order bit this instruction reads out the internal status of the NJU6631A. when this instruction is executed, the busy flag (bf) which indicate internal operation is read out from db 7 and the address of cg ram or dd ram is read out from db 6 to db 0 (the address for cg ram or dd ram is determined by the previous instruction). (bf)=1 indicates that internal operation is in progress. the next instruction is inhibited when (bf)=1. check the (bf) status before the next write operation. (k) write data to cg or dd ram rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 d d d d d d d d (dd ram) higher order bit lower order bit rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 0 * * * d d d d d (cg ram) higher order bit lower order bit write data to cg ram or dd ram instruction is executed when the code "1" is written into (rs) and code "0" is written into (r/w). by the execution of this instruction, the binary 5-bit data "ddddd" are written into the cg ram, and the binary 8-bit data "dddddddd" are written into the dd ram. the selection of the cg ram or dd ram is determined by the previous instruction. after this instruction execution, the address increment (+1) or decrement (-1) performed automatically according to the entry mode set. and the display shift is also executed according to the previous entry mode set. (l) read data from cg or dd ram rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 1 d d d d d d d d (dd ram) higher order bit lower order bit rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 code 1 1 * * * d d d d d (cg ram) higher order bit lower order bit read data from cg ram or dd ram instruction is executed when the code "1" is written into (rs) and (r/w). by the execution of this instruction, the binary 5 bit data "ddddd" are read out from cg ram, and the binary 8 bit data "dddddddd" are read out from dd ram. the selection of the cg ram or dd ram is determined by the previous instruction. before executing this instruction, either the cg ram address set or dd ram address set must be executed, otherwise the first read out data are invalidated. when this instruction is serially executed, the next address data is normally read from the second read. the address set instruction is not required if the cursor shift instruction is executed just beforehand (only dd ram reading). the cursor shift instruction has same function as the dd ram address set, so that after reading the dd ram, the address increment or decrement is executed automatically according to the entry mode. but display shift does not occur regardless of the entry mode. note : the address counter(ac) is automatically incremented or decremented by 1 after write instructions to either of the cg ram or dd ram. even if the read instruction is executed after this instruction, the addressed data can not be read out correctly. for a correct data read out, either the address set instruction or cursor shift instruction (only with dd ram) must be implemented just before this instruction or from the second time read out instruction execution if the read out instruction is executed 2 times consecutively.
NJU6631A (3-2) initialization using the internal reset circuits (a) 16-character 1-line in 8-bit operation addressing mode 1 (using internal reset circuits). at the 16-character 1-line display, the function set, display on/off control and entry set instruction must be executed before the data input, as shown below. since the display shift operation changes only display position and the dd ram contents remain unchanged, display data which are entered first can be output when the return home operation is performed. power on initialized. no display appears. rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 function set 0 0 0 0 1 1 0 * 0 0 set the 8-bit operation, 16- character 1-line display, pin configuration mode a, addressing mode 1. disp. on/off control 0 0 0 0 0 0 1 1 1 0 turns on display and cursor. entire display is in space mode by the initialization. entry mode set 0 0 0 0 0 0 0 1 1 0 example for set address increment and cursor right shift when the data write to the dd or cg ram. write data to the dd/cg ram and se t the instruction (b) 8-character 2-line in 4-bit operation addressing mode 2 (using internal reset circuits). in the 4-bit operation, the function set must be performed by the user programming. when the power is turned on, 8-bit operation is selected automatically, therefore the first input is performed under 8-bit operation. in this operation, full instruction can not input because of terminals db 0 to db 3 are no connection. therefore, same instruction must be rewritten on the rs, r/w and db 7 to db 4 , as shown below. since one operation is completed by the two accesses in the 4-bit operation mode, rewrite is required to set the instruction code in full. 8-character 2-line in 4-bit operation is shown as follows: power on initialized. no display appears. rs r/w db 7 db 6 db 5 db 4 function set 0 0 0 0 1 0 set the 4-bit operation. this step is executed in 8-bit mode set by the initialization. function set 0 0 0 0 0 1 0 * 1 1 0 1 set the 4-bit operation / 2-line 8-character display / pin configuration mode b / addressing mode 2. the 4-bitoperation starts from this step. disp. on/off control 0 0 0 0 0 1 0 1 0 1 0 0 turn on display and cursor. entire display is in space mode by the initialization. entry mode set 0 0 0 0 0 0 0 1 0 1 0 0 example for set address increment and cursor right shift when the data write to the dd or cg ram. write data to the dd/cg ram and se t the instruction
NJU6631A (3-3) initialization by instruction if the power supply conditions for the correct operation of the internal reset circuits are not met, the NJU6631A must be initialized by the instruction. (a) initialization by instruction in 8-bit interface power on initialized. no display appears. wait more than 15ms after v dd rises to 4.5v rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 function set 0 0 0 0 1 1 * * * * function set (8-bit interface length) wait more than 4.1ms function set 0 0 0 0 1 1 * * * * function set (8-bit interface length) wait more than 100us rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 function set 0 0 0 0 1 1 * * * * function set (8-bit interface length) busy flag(bf) can not be checked before this step, but it can be checked after this step. after this step, busy flag(bf) check or longer waiting time than each instruction execution time is required. rs r/w db 7 db 6 db 5 db 4 db 3 db 2 db 1 db 0 function set 0 0 0 0 1 1 1 * 0 0 set the 8-bit operation, 16- character 1-line, pin configuration mode a, addressing mode 2. display off 0 0 0 0 0 0 1 0 0 0 display clear 0 0 0 0 0 0 0 0 0 1 entry mode set 0 0 0 0 0 0 0 1 1 0 example for set address increment and cursor right shift when the data write to the dd or cg ram. write data to the dd/cg ram and se t the instruction
NJU6631A (b) initialization by instruction in 4-bit interface power on initialized. no display appears. wait more than 15ms after v dd rises to 4.5v rs r/w db 7 db 6 db 5 db 4 function set 0 0 0 0 1 1 function set (8-bit interface length) wait more than 4.1ms function set 0 0 0 0 1 1 function set (8-bit interface length) wait more than 100us function set 0 0 0 0 1 1 function set (8-bit interface length) busy flag (bf) can not be checked before this step, but it can be checked after this step. after this step, busy flag (bf) check or longer waiting time than each instruction execution time is required. function set 0 0 0 0 1 1 function set in 8-bit interface length. (set 4-bit interface length) 0 0 0 0 0 0 0 * 1 0 0 0 set the 4-bit operation, 16-character 1-line, pin configuration mode a, addressing mode 1. display off 0 0 0 0 0 1 0 0 0 0 0 0 display clear 0 0 0 0 0 0 0 0 0 0 0 1 entry mode set 0 0 0 0 0 0 0 1 0 1 0 0 example for set address increment and cursor right shift when the data write to the dd or cg ram. write data to the dd/cg ram and se t the instruction
NJU6631A (4) lcd display (4-1) power supply for lcd driving NJU6631A incorporates bleeder resistance to generate the lcd display driving waveform. the bleeder resistance is set 1/5 bias suitable for 1/18 duty ratio and 1.5k ? per resistance. furthermore, the bias level can be changed by connecting external resistance between the v 2 , v 3 terminals, if needed. table 5. lcd driving voltage vs duty ratio duty ratio 1/16 bias 1/5 v 2 v dd -2/5v lcd v 3 v dd -3/5v lcd power supply v 5 v dd -v lcd note) power on or power off is in the following order. power on : v 5 should be turned on after the v dd turned on or at the same time. power off : v 5 should be turned off before the v dd turned off or at the same time. (4-2) relation between oscillation frequency and lcd frame frequency. lcd frame frequency example mentioned below is based on 270khz oscillation. the clock for the lcd driving is using 270khz (1 clock=3.7us). 1/16 duty 1 frame=3.7(us)x40x16x4=9,472(ms) frame frequency=1/9,472(ms)=105.6(hz) v 2 v 3 v 5 r 1 r 1 r 1 r 1 r 1 v 5 v 4 v 3 v 2 v 1 v dd v dd v lcd NJU6631A internal v 5 v 4 v 3 v 2 v 1 v dd 1 2 3 4 16 1 2 3 4 16 1 2 3 40 clock 1 frame 1 frame
NJU6631A interface with mpu NJU6631A can be interfaced with both of 4/8 bit mpu and the two-time 4-bit or one-time 8-bit data transfer is available. (1) when the interface length is 4-bit, the data transfer is performed by 4 lines connected to db 4 to db 7 (db 0 to db 3 are not used). the data transfer with the mpu is completed by the two-time 4-bit data transfer. the data transfer is executed in the sequence of upper 4-bit (the data db 4 to db 7 at 8-bit length) and lower 4-bit (the data db 0 to db 3 at 8-bit length). the busy flag check must be executed after two-time 4-bit data transfer (1 instruction execution). in this case the data of busy flag and address counter are also output twice. ir 7 ir 3 bf ac 3 dr 7 dr 3 rs r/w e ir 6 ir 2 ac 6 ac 2 dr 6 dr 2 ir 5 ir 1 ac 5 ac 1 dr 5 dr 1 ir 4 ir 0 ac 4 ac 0 dr 4 dr 0 db 7 db 6 db 5 db 4 writing instruction into instruction register (ir) read out busy flag (bf) and address counter (ac) read out data register (dr) ir 7 bus ac 3 no bus rs r/w e internal status db 7 operation instruction writing busy flag check instruction writing busy flag check ir 3 ac 3 d 7 d 3
NJU6631A (2) 8-bit mpu interface data bus bus no bus data rs r/w e internal status db 7 operation writing instruction into instruction register (ir) busy flag check writing instruction into instruction register (ir) busy flag check busy flag check
NJU6631A absolute maximum ratings (ta=25 c) parameter symbol ratings unit supply voltage v dd -0.3 ~ +7.0 v input voltage v in -0.3 ~ v dd + 0.3 v operating temperature t opr -30 ~ +80 c storage temperature t stg -55 ~ +125 c note 1) if the lsi are used on condition above the absolute maximum ratings, the lsi may be destroyed. using the lsi within electrical characteristics is strongly recommended for normal operation. use beyond the electric characteristics conditions will cause malfunction and poor reliability. note 2) all voltage values are specified as v ss =0v. note 3) the relation : v dd >v 5 v 5out , v ss =0v must be maintained. turn on v dd first then turn on v 5 must be required. note 4) decoupling capacitor should be connected between v dd and v ss due to the stabilized operation for the lsi. electrical characteristics (v dd =5.0v 10%, v ss =0v, ta= -20~75 c) parameter symbol conditions min typ max unit note operating voltage v dd 4.5 5.0 5.5 v v ih1 2.3 - v dd 1 v il1 all input/output terminals except osc and e terminals - - 0.8 v ih2 v dd -1.0 - v dd 2 v il2 only osc terminal - - 1.0 v ih3 0.8v dd v dd input voltage 3 v il3 only e terminal - - 0.2v dd v 5 v oh -i oh =0.205ma 2.4 - - output voltage v ol i ol =1.6ma - - 0.4 v 6 driver on-resist.(com) r com id=50ua(all com term.) - - 20 k ? 9 driver on-resist.(seg) r seg id=50ua(all seg term.) - - 30 k ? 9 input leakage current i li v in =0cv dd -1 - 1 ua 7 pull-up resist. current -ip v dd =5v 50 125 250 ua operating current i dd cr oscillation v dd =5v, f osc =270khz - 1.0 1.8 ma 8 v 2 2.7 3.0 3.3 lcd driving voltage v 3 ta=25 c, v dd =5v, v 5 =0v measurement terminal is seg. 1.7 2.0 2.3 v bleeder resistance r b v dd -v 5 =5v ta=25 c 6.65 9.5 12.35 k ? oscillation frequency f osc v dd =5v, ta=25 c 135 270 405 khz lcd driving voltage v lcd v 5 terminal, v dd =5v v dd -3 - v dd -5 v 10
NJU6631A note 5) input / output structure except lcd driver are shown below : -input terminal structure e terminal rs, r/w, reset terminals -input / output terminal structure db 0 ~ db 7 note 6) apply to the input / output terminal. note 7) except pull-up resistance current and output driver current. note 8) except input/output current but including the current flow on bleeder resistance. note 9) r com and r seg are the resistance values between power supply terminals(v dd ,v 2 ,v 3 ,v 5 ) and each common terminal (com 1 ~com 16 ), and supply voltage (v dd ,v 2 ,v 3 ,v 5 ) and each segment terminal (seg 1 ~seg 40 ) respectively, and measured when the current id is flown on every common and segment terminals at a same time. note 10) apply to the output voltage from each com and seg are less than 0.15v against the lcd driving constant voltage(v dd , v 5 ) at no load condition. -bleeder resistance v dd pmos nmos v ss v dd pmos nmos v ss v dd pmos v dd pmos nmos v dd pmos v ss v dd pmos nmos enable data r 1 r 1 r 1 r 1 r 1 v 5 v 4 v 3 v 2 v 1 v dd NJU6631A internal v 2 v 3 v 5
NJU6631A bus timing characteristics -write operation sequence (write from mpu to NJU6631A) (v dd =5.0v 10%, v ss =0v, ta=-20~75 c) parameter symbol min. max. condition unit enable cycle time t cyce 500 - ns ?high? level pw eh 220 - ns enable pulse width ?low? level pw el 280 - ns enable rise time, fall time t er, t ef - 20 ns set up time rs, r/w-e t as 40 - ns address hold time t ah 10 - ns data set up time t dsw 60 - ns data hold time t h 10 - fig.1 ns timing characteristics (write operation) fig. 1 the timing characteristics of the bus write operating sequence. (write from mpu to NJU6631A) rs r/w e db 0 db 7 v ih1 v ih1 v il1 v il1 v il1 v il1 t as t am v ih3 v il3 v ih3 v il3 v il3 t am pw eh t ef t er t dsw t h v ih1 v il1 v ih1 v il1 pw el t cyce valid data
NJU6631A -read operation sequence (read from NJU6631A to mpu) (v dd =5.0v 10%, v ss =0v, ta=-20~75 c) parameter symbol min. max. condition unit enable cycle time t cyce 500 - ns ?high? level pw eh 220 - ns enable pulse width ?low? level pw el 280 - ns enable rise time, fall time t er, t ef - 20 ns set up time rs, r/w-e t as 40 - ns address hold time t ah 10 - ns data delay time t ddr - 240 ns data hold time t dhr 20 - fig.2 ns -db 0 ~db 7 load condition : cl=100pf timing characteristics (read operation) fig. 2 the timing characteristics of the bus read operating sequence. (read from NJU6631A to mpu) rs r/w e db 0 db 7 v ih1 v ih1 v il1 v il1 t as t am v ih3 v il3 v ih3 v il3 v il3 t am pw eh t ef t er t ddr t dhr v oh1 v ol1 v oh1 v ol1 pw el t cyce valid data v ih1 v ih1
NJU6631A -the input condition when using the hardware reset circuit parameter symbol condition min. typ. max. unit reset input ?l? level width t rsl f osc =270khz 1.2 - - ms input timing fig. 3 the timing characteristics of the hardware reset input ? power supply condition when using the internal initialization circuit (ta=-20 to 75 c) p a r a m e t e r symbol condition min typ max unit power supply rise time t rdd ? 0.1 ? 5 ms power supply off time t off ? 1 ? ? ms 0.1ms ! t rdd ! 10ms t off 1ms note.) since the internal initialization circuits will not operate normally unless the above conditions are met, in such a case initialize by instruction(refer to initialization by the instruction). reset t rsl *t off specifies the power off time in a short period off or cyclical on/off 0.2 0.2 4.5 3v v dd t rdd t off
NJU6631A lcd driving waveform 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v dd v 1 v 2 v 3 v 4 v 5 com 1 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 com 16 v dd v 1 v 2 v 3 v 4 v 5 com 2 v dd v 1 v 2 v 3 v 4 v 5 com 16 v dd v 1 v 2 v 3 v 4 v 5 seg 1 v dd v 1 v 2 v 3 v 4 v 5 seg 2
NJU6631A application circuits (1) lcd display interface pin configuration mode a (bottom view) mode a, 16-character 1-line display example (m0=0, m1=0) mode a, 8-character 2-line display example (m0=0, m1=1) seg 1 20 40 21 21 40 20 1 lcd panel (16-character 1-line) seg 1 com 8 com 1 seg 20 seg 21 seg 40 com 16 com 9 NJU6631A bottom view lcd panel (8-character 2-line) seg 1 com 8 com 1 seg 20 seg 21 seg 40 com 16 com 9 NJU6631A bottom view
NJU6631A application circuits (2) lcd display interface pin configuration mode b (top view) mode b, 16-character 1-line display example (m0=1, m1=0) mode b, 8-character 2-line display example (m0=1, m1=1) seg 1 20 40 21 21 40 20 1 lcd panel (16-character 1-line) seg 1 com 8 com 1 seg 20 seg 21 seg 40 com 16 com 9 NJU6631A top view lcd panel (8-character 2-line) seg 1 com 8 com 1 seg 20 seg 21 seg 40 com 16 com 9 NJU6631A top view
m e m o [caution] the specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. the application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.

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